Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photosensor, e.g. a photogate, photoconductor, or a photodiode. In a CMOS imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photosensor converts photons to electrons which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photosensor to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, each assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
In a digital CMOS imager, when incident light strikes the surface of a photodiode photosensor, electron/hole pairs are generated in the p-n junction of the photodiode. The generated electrons are collected in the n-type region of the photodiode. The photo charge moves from the initial charge accumulation region to the floating diffusion region or the charge may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by a source follower transistor.
Conventional CMOS imagers typically have difficulty transferring all of the photogenerated charge from the photodiode to the floating diffusion region. One problem with transferring charge occurs when the n-type silicon layer of the photodiode is located close to the surface; this causes electron/carrier recombination due to surface defects. There is a need to reduce this electron/carrier recombination to achieve good charge transfer to the floating diffusion region. Another obstacle hindering “complete” charge transference includes potential barriers that exist at the gate of a transfer transistor.
Additionally, conventional CMOS imager designs provide only approximately a fifty percent fill factor, meaning only half of the pixel is utilized in converting light to charge carriers. As shown in FIG. 1, a top plan view of a conventional CMOS pixel sensor cell, only a small portion of the cell comprises a photosensor (photodiode) 49. The remainder of the cell includes the floating diffusion region 14, coupled to a transfer gate 18, and source/drain regions 55 for reset, source follower, and row select transistors having respective gates 19, 24, and 25. It is desirable to increase the fill factor of the conventional cell.
Digital imagers may utilize a pixel containing a p-n-p photodiode 49 as the photo-conversion device. An example of this design is shown in FIG. 2, a cross-sectional view of the pixel of FIG. 1, taken along line A-A′. The pixel sensor cell shown in FIG. 2 has a p-type substrate 60 with a p-well 61. In the illustrated example, a p-type region 10 of photodiode 49 is located closest to the surface of substrate 60 and an n-type region 12 is buried between the p-type region 10. The p-n-p photodiode 49 has some drawbacks. First, there can be a lag problem since the pixel uses a transfer transistor 18 for transferring charge to the floating diffusion region 14. Lag occurs because during integration the electron carriers are collected in the sandwiched n-type region 12 and then transferred to the floating diffusion region 14 through a transfer gate 18. In order to fully utilize the generated electron carrier, it is necessary to eliminate two energy barriers to reach the floating diffusion region 14 (i.e., there is one barrier between the photodiode 49 and the transfer gate 18 and another barrier between the transfer gate 18 and floating diffusion region 14). Next, charge leakage is another problem associated with the conventional p-n-p photodiode 49. One source of such leakage occurs when the transfer transistor 18 gate length is too short, causing sub-threshold current to become significantly high due to charge breakdown between n-type regions on both sides of the transfer gate channel.
Additionally, as the total area of pixels continues to decrease (due to desired scaling), it becomes increasingly important to create high sensitivity photosensors that utilize a minimum amount of surface area. Raised photodiodes have been proposed as a way to increase the fill factor and optimize the sensitivity of the CMOS pixel by increasing the sensing area of the cell without increasing the surface area of the substrate. Further, raising the photodiode increases the quantum efficiency of the cell by bringing the sensing region closer to the microlens. However, raised photodiodes, such as described in U.S. application Ser. No. 10/443,891, assigned to Micron Technology, Inc., and incorporated herein by reference, also have problems with leakage current across the elevated p-n junctions. Accordingly, a raised photosensor that reduces this leakage, while increasing the quantum efficiency of the pixel cell, is desired.